Advanced VLSI
Summer School 2023

Welcome to Ambarella’s
Advanced VLSI Summer School!


11th-15th, 2023


University of Parma,
South Campus

This program provides an exclusive chance to explore the captivating realm of ASIC/SoC design.

It offers a well-rounded curriculum that covers both theoretical and hands-on aspects, delivered by industry experts. Participants will gain a comprehensive understanding of the entire design process, with a specific emphasis on advanced computer architectures, RTL coding, debugging and logic synthesis.

Additionally, the program features immersive lab sessions where students actively engage in designing and implementing a fully functional pipelined RISC-V RV32I core. Throughout the process, they will progress from specifications to post-synthesis netlist, acquiring valuable practical experience.

The goal of the course is to teach students how to go from specifications to netlist of a complex digital circuit.
Students will learn:

  • How front-end and back-end design flows are structured.

  • Principles of micro-architecture and power, performance, area (PPA) trade-offs.

  • Memory hierarchy.

  • RTL (SystemVerilog) coding of the design and its functional verification through simulation.

  • Synthesis, timing analysis and logic equivalence checks (LEC) using industry standard EDA tools.

  • Advanced topics such as out-of-order execution, parallel data processing, etc.

Lessons will be led by engineers from Ambarella, a Silicon Valley fabless chipmaker, currently designing award winning 5nm SoCs for autonomous driving, integrating deeplearning and computer vision accelerators, based on 30 years of VisLab research in the field currently working on complex 5nm SoCs.

Instructors will bring their practical industry knowledge directly into the classroom, providing valuable insights and guidance to the participants.


The course will take place September 11th – 15th, 2023 at the University of Parma, South Campus.
Theory lessons will be in the morning (9-13), while lab sessions will be in the afternoon (14-18). All the lessons will be in English.

Course Outline

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    Day 1 - A Single-cycle RISC-V Core

    • Introduction
    • ASIC Design Overview
    • RV32I ISA
    • Single-cycle Core Microarchitecture
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    Day 2 - A Pipelined RISC-V Core

    • Introduction to Pipelined Designs
    • Pipelined Core Microarchitecture
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    Day 3 - Memory Hierarchy

    • Hierarchy of storage and technologies
    • Caches
    • Virtual Memory
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    Day 4 - Synthesis and Timing Analysis

    • Logic Synthesis
    • Static Timing Analysis
    • Logic Equivalent Checking
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    Day 5 - Advanced Microarchitectures

    • Custom RISC-V Instructions
    • Out-of-order execution
    • Vector Processors (real-world example from Ambarella)
    • Case study: Ambarella Neural vector Processor
    • Final Exam


This Summer School is designed for individuals who possess a solid foundation in electronics and/or computer engineering.

To ensure the best learning experience, we require participants to meet one essential prerequisite, which is to be enrolled in either a PhD or Master Course in electronics or computer engineering. Familiarity with basic concepts of digital design, computer architecture, and low-level programming will be advantageous for successfully engaging with the course material.


The VLSI Summer School is offered to all eligible applicants free of charge; eligibility is based on the academic curriculum and the possession of the prerequisites listed above.
Hotel accommodation for attendees coming from other cities will be offered at no charge upon request.


To apply please follow this link or fill in the form below.

The deadline is 31 Aug. 2023, but early application is strongly advised, especially for those asking for accommodation support.
The maximum number of participants for this school is 20, so hurry up!


You can request information by sending an email to

Request informations